1. Field of the Invention
The present invention relates to a clock generator, and more particularly, to a clock generator for controlling memory and a method of generating a clock signal.
2. Description of the Related Art
Similar to signal processing application products including modems and the like, in a semiconductor chip having a program memory therein, a signal processor must output an instruction stored in the program memory within a clock cycle of a system clock. However, errors occur in the timing of control signals input from the signal processor to the program memory if conditions for a process are changed or simulation for circuits in the semiconductor chip are not accurate. As a result, errors may occur when the instruction of the program memory is read.
FIG. 1 is a block diagram of a signal processing semiconductor chip having a conventional program memory. The signal processing semiconductor chip 100 includes a processor 110 and a program memory unit 120. Here, the processor 110 is a signal processor, and in particular, a digital signal processor (DSP). In general, memory is classified into memory for storing data and memory for storing instructions, i.e., a code signal. Here, the program memory unit 120 is memory for storing an instructions.
The processor 110 transmits control signals CSN, OEN, and ADD to the program memory unit 120 in response to a system clock SYSCLK and reads an instruction DO stored in the program memory unit 120. The control signals CSN, OEN, and ADD includes a chip select signal CSN, an output enabling signal OEN, and an address signal ADD.
FIG. 2 is a timing diagram of control signals output from the processor 110 shown in FIG. 1. Referring to FIGS. 1 and 2, the processor 110 outputs the control signals CSN, OEN, and ADD in response to the system clock SYSCLK. FIG. 2 shows the timing relationship between the address signal ADD and the output enabling signal OEN.
The address signal ADD is delayed by a predetermined time tD in response to a rising edge of the system clock SYSCLK. The output enabling signal OEN is also delayed by a delay time tD since it is simultaneously generated with the address signal ADD. Delay time for the control signals OEN and ADD increases if the control signals OEN and ADD that are delayed are applied to the program memory unit 120.
FIG. 3 is a timing diagram of the control signals of FIG. 1 applied to the program memory unit 120. Referring to FIG. 3, timing of the system clock SYSCLK is controlled by delaying the system clock SYSCLK so that the rising edge of the system clock SYSCLK recognizes the address signal ADD. That is, the system clock SYSCLK is delayed so that the program memory unit 120 operates without errors. Thus, the address signal ADD has an operational margin by an operational margin time tAD.
FIG. 4 is a timing diagram showing the operation of the program memory unit 120 shown in FIG. 1. Referring to FIG. 4, the system clock SYSCLK is sufficiently delayed so that the program memory unit 120 can operate properly. That is, the chip select signal CSN and the address signal ADD operate with sufficient setup time and hold time in response to the rising edge of the system clock SYSCLK. The time periods tCS and tAS both represent setup time for the rising edge of the system clock SYSCLK, and tCH and tAH both represent hold time for the rising edge of the system clock SYSCLK. The program memory unit 120 generates an instruction DO stored therein in response to the control signals CSN, OEN, ADD. The period tDH represents hold time for the rising edge of the system clock SYSCLK, a portion with slanted lines represents an unknown instruction, and tACC represents the time required for generating a valid instruction DO from the rising edge of the system clock SYSCLK.
The system clock SYSCLK must be delayed by the sum of the delay time tD of FIG. 2 and the operational margin time tAD of FIG. 3 in order to normally operate the program memory unit 120 as shown in FIG. 4. The time required for delaying the system clock SYSCLK depends on a simulation. Thus, the time required for delaying the system clock SYSCLK is inaccurate if the simulation is inaccurate. As a result, errors may occur when the instruction is read from the program memory unit 120.
To solve the above-described problems, it is a first object of the present invention to provide a semiconductor memory device in which the delay of a system clock for controlling a program memory is automatically controlled to optimize the speed for reading the program memory.
It is a second object of the present invention to provide a method of optimizing the speed for reading a program memory by automatically controlling the delay of a system clock for controlling the program memory.
In accordance with the invention, there is provided a semiconductor memory device including a processor, a program memory unit, and a clock generator. The processor generates control signals for controlling the program memory unit in response to a system clock, receives an instruction from the program memory unit, and is reset in response to a reset signal. The program memory unit receives the control signals and generates the instruction in response to a clock signal. The clock generator receives the control signals and the instruction in response to the system clock and generates the clock signal for controlling the program memory unit and the reset signal for resetting the processor.
In one embodiment, the clock generator includes a mirror memory, a comparator, a counter, a delayer, and a reset delayer. The mirror memory receives the control signals and generates a mirror instruction in response to the clock signal. The comparator is reset in response to the reset signal, compares the mirror instruction with the instruction in response to the system clock, outputs a comparison reset signal at a first logic level if the mirror instruction and the instruction have different phases, and outputs the comparison reset signal at a second logic level if the mirror instruction and the instruction have the same phase. The counter receives the comparison reset signal and increases an output value if the comparison reset signal is at the first logic level. The delayer delays the system clock and outputs it as the clock signal in response to the output value of the counter. The reset delayer receives the comparison reset signal in response to the system clock and generates the reset signal if the comparison reset signal is at the first logic level.
In accordance with another aspect of the invention, there is provided a method of generating a clock signal for controlling a program memory unit in a semiconductor memory device which uses the program memory unit to store an instruction and a processor for generating control signals for controlling the program memory unit. The method includes: (a) generating control signals for controlling the program memory unit in response to a system clock; (b) receiving the control signals and generating the instruction in response to a predetermined clock signal; (c) receiving the control signals and the instruction in response to the system clock and generating the clock signal for controlling the program memory unit and a reset signal for resetting the processor; and (d) receiving the instruction, resetting the processor in response to the reset signal, and going back to step (a) to continue the method.
As described, in a semiconductor memory device having a clock generator according to the present invention and a method of generating a clock, the speed for reading an instruction of a program memory unit is prevented from being inaccurate due to a change in conditions for a process and the inaccuracy of simulation. Also, the delay of a system clock for controlling the program memory unit is automatically controlled. Thus, the speed for reading the instruction of the program memory unit is optimized.